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DATA SHEET
1GB Registered DDR SDRAM DIMM
HB54R1G9F2-A75B/B75B/10B (128M words x 72 bits, 2 Banks)
Description
The HB54R1G9F2 is a 128M x 72 x 2 bank Double Data Rate (DDR) SDRAM Module, mounted 36 pieces of 256Mbits DDR SDRAM (HM5425401BTB) sealed in TCP package, 1 piece of PLL clock driver, 2 pieces of register driver and 1 piece of serial EEPROM (2k bits EEPROM) for Presence Detect (PD). Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2-bit prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. An outline of the products is 184-pin socket type package (dual lead out). Therefore, it makes high density mounting possible without surface mount technology. It provides common data inputs and outputs. Decoupling capacitors are mounted beside each TCP on the module board. Note: Do not push the cover or drop the modules in order to protect from mechanical defects, which would be electrical defects.
Features
* 184-pin socket type package (dual lead out) Outline: 133.35mm (Length) x 43.18mm (Height) x 4.80mm (Thickness) Lead pitch: 1.27mm * 2.5V power supply (VCC/VCCQ) * SSTL-2 interface for all inputs and outputs * Clock frequency: 143MHz/133MHz/125MHz (max.) * Data inputs and outputs are synchronized with DQS * 4 banks can operate simultaneously and independently (Component) * Burst read/write operation * Programmable burst length: 2, 4, 8 Burst read stop capability * Programmable burst sequence Sequential Interleave * Start addressing capability Even and Odd * Programmable /CAS latency (CL): 3, 3.5 * 8192 refresh cycles: 7.8s (8192/64ms) * 2 variations of refresh Auto refresh Self refresh
Document No. E0089H40 (Ver. 4.0) Date Published August 2002 (K) Japan URL: http://www.elpida.com Elpida Memory, Inc. 2001-2002 Hitachi, Ltd. 2000 Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
HB54R1G9F2-A75B/B75B/10B
Ordering Information
Part number HB54R1G9F2-A75B*1 HB54R1G9F2-B75B*2 HB54R1G9F2-10B* Clock frequency MHz (max.) 133 133 100 /CE latency 3.0 3.5 3.0 Package Contact pad
184-pin dual lead out socket Gold type
Notes: 1. 143MHz operation at /CAS latency = 3.5. 2. 100MHz operation at /CAS latency = 3.0. 3. 125MHz operation at /CAS latency = 3.5.
Pin Configurations
Front side 1 pin 52 pin 53 pin 92 pin
93 pin Back side
144 pin 145 pin 184 pin
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
Pin name VREF DQ0 VSS DQ1 DQS0 DQ2 VCC DQ3 NC /RESET VSS DQ8 DQ9 DQS1 VCCQ NC NC VSS DQ10 DQ11 CKE0 VCCQ DQ16 DQ17 DQS2 VSS A9 DQ18
Pin No. 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74
Pin name DQS8 A0 CB2 VSS CB3 BA1 DQ32 VCCQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 VCCQ /WE DQ41 /CAS VSS DQS5 DQ42 DQ43 VCC NC DQ48 DQ49 VSS
Pin No. 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
Pin name VSS DQ4 DQ5 VCCQ DM0/DQS9 DQ6 DQ7 VSS NC NC NC VCCQ DQ12 DQ13 DM1/DQS10 VCC DQ14 DQ15 CKE1 VCCQ NC DQ20 A12 VSS DQ21 A11 DM2/DQS11 VCC
Pin No. 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166
Pin name VSS DM8/DQS17 A10 CB6 VCCQ CB7 VSS DQ36 DQ37 VCC DM4/DQS13 DQ38 DQ39 VSS DQ44 /RAS DQ45 VCCQ /S0 /S1 DM5/DQS14 VSS DQ46 DQ47 NC VCCQ DQ52 DQ53
Data Sheet E0089H40 (Ver. 4.0)
2
HB54R1G9F2-A75B/B75B/10B
Pin No. 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Pin name A7 VCCQ DQ19 A5 DQ24 VSS DQ25 DQS3 A4 VCC DQ26 DQ27 A2 VSS A1 CB0 CB1 VCC Pin No. 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Pin name NC NC VCCQ DQS6 DQ50 DQ51 VSS VCCID DQ56 DQ57 VCC DQS7 DQ58 DQ59 VSS NC SDA SCL Pin No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 Pin name DQ22 A8 DQ23 VSS A6 DQ28 DQ29 VCCQ DM3/DQS12 A3 DQ30 VSS DQ31 CB4 CB5 VCCQ CK0 /CK0 Pin No. 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Pin name NC VCC DM6/DQS15 DQ54 DQ55 VCCQ NC DQ60 DQ61 VSS DM7/DQS16 DQ62 DQ63 VCCQ SA0 SA1 SA2 VCCSPD
Data Sheet E0089H40 (Ver. 4.0)
3
HB54R1G9F2-A75B/B75B/10B
Pin Description
Pin name A0 to A12 BA0, BA1 DQ0 to DQ63 CB0 to CB7 /RAS /CAS /WE /S0, /S1 CKE0, CKE1 CK0 /CK0 DQS0 to DQS8 DM0 to DM8/DQS9 to DQS17 SCL SDA SA0 to SA2 VCC VCCQ VCCSPD VREF VSS VCCID /RESET NC Function Address input Row address Column address A0 to A12 A0 to A9, A11
Bank select address Data input/output Check bit (Data input/output) Row address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input and output data strobe Input and output data strobe Clock input for serial PD Data input/output for serial PD Serial address input Power for internal circuit Power for DQ circuit Power for serial EEPROM Input reference voltage Ground VCC identification flag Reset pin (forces register inputs low) No connection
Data Sheet E0089H40 (Ver. 4.0)
4
HB54R1G9F2-A75B/B75B/10B
Serial PD Matrix*
Byte No. 0 1 2 3 4 5 6 7 8 9
1
Function described Number of bytes utilized by module manufacturer Total number of bytes in serial PD device Memory type Number of row address Number of column address Number of DIMM banks Module data width Module data width continuation
Bit7 1 0 0 0 0 0 0 0
Bit6 0 0 0 0 0 0 1 0 0 1 1 0
Bit5 Bit4 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0
Bit3 0 1 0 1 1 0 1 0 0 0 0 0
Bit2 0 0 1 1 0 0 0 0 1 0 1 0
Bit1 Bit0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 0
Hex value 80 08 07 0D 0B 02 48 00 04 70 75 80
Comments 128 256 byte SDRAM DDR 13 11 2 72 bits 0 (+) SSTL 2.5V CL = 2.5*5
Voltage interface level of this assembly 0 DDR SDRAM cycle time, CL = X -A75B -B75B -10B 0 0 1
10
SDRAM access from clock (tAC) -A75B/B75B -10B
0
1 0 1 0 0 0 0 0 0 0 0 0 1 0 1
1
0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
1
0 0 0 0 0 0 0 0 0 0 0 1 0 1 1
1
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
0
0 0 0 0 0 0 1 0 1 0 0 0 0 0 0
1
0 0 0 1 1 0 1 1 1 0 0 1 0 1 0
0
0 1 1 0 0 0 1 0 0 0 1 1 0 0 0
1
0 0 0 0 0 1 0 0 0 1 0 0 0 1 0
75
80 02 82 04 04 01 0E 04 0C 01 02 26 C0 75 A0
0.75ns*
0.8ns*5 ECC
5
11 12 13 14 15 16 17 18 19 20 21 22 23
DIMM configuration type Refresh rate/type Primary SDRAM width Error checking SDRAM width SDRAM device attributes: Minimum clock delay back-to-back column access SDRAM device attributes: Burst length supported SDRAM device attributes: Number of banks on SDRAM device SDRAM device attributes: /CAS latency SDRAM device attributes: /CS latency SDRAM device attributes: /WE latency SDRAM module attributes SDRAM device attributes: General Minimum clock cycle time at CLX - 0.5 -A75B -B75B/10B
7.8 s Self refresh x4 x4 1 CLK 2, 4, 8 4 2, 2.5 0 1 Registered 0.2V CL = 2*5
24
Maximum data access time (tAC) from 0 clock at CLX - 0.5 -A75B/B75B -10B 1 Minimum clock cycle time at 0 CLX - 1 Maximum data access time (tAC) from 0 clock at CLX - 1 Minimum row precharge time (tRP) 0
1
0 0 0 1
1
0 0 0 0
1
0 0 0 1
0
0 0 0 0
1
0 0 0 0
0
0 0 0 0
1
0 0 0 0
75
80 00 00 50
0.75ns*
0.8ns*5
5
25 26 27
20ns
Data Sheet E0089H40 (Ver. 4.0)
5
HB54R1G9F2-A75B/B75B/10B
Byte No. 28 29 30 Function described Minimum row active to row active delay (tRRD) Minimum /RAS to /CAS delay (tRCD) Minimum active to precharge time (tRAS) -A75B/B75B -10B 31 32 Module bank density Address and command setup time before clock (tIS) -A75B/B75B -10B 33 Bit7 0 0 0 0 1 1 1 Bit6 0 1 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 Bit5 Bit4 1 0 1 1 0 0 1 0 1 0 1 0 1 0 0 0 0 0 1 1 0 1 0 1 1 1 1 1 0 1 0 0 0 0 0 1 Bit3 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Bit2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Bit1 Bit0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 Hex value 3C 50 2D 32 80 90 B0 90 B0 50 60 50 60 00 41 46 4B 50 Comments 15ns 20ns 45ns 50ns 2 banks 512MB 0.9ns*5 1.1ns*5 0.9ns*5 1.1ns*5 0.5ns*5 0.6ns*5 0.5ns*5 0.6ns*5 Future use 65ns*5 70ns*5 75ns*5 80ns*5
Address and command hold time after 1 clock (tIH) -A75B/B75B -10B 1 0 0 0 0 0 0 0 0 0 Data input setup time before clock (tDS) -A75B/B75B -10B Data input hold time after clock (tDH) -A75B/B75B -10B
34
35
36 to 40 41
Superset information Active command period (tRC) -A75B/B75B -10B Auto refresh to active/ Auto refresh command cycle (tRFC) -A75B/B75B -10B
42
43 44
SDRAM tCK cycle max. (tCK max.) Dout to DQS skew -A75B/B75B -10B Data hold skew (tQHS) -A75B/B75B -10B
0
0 0 0 1 0 0 0 0 1 0 0 x 0 0 0
0
0 0 1 0 0 0 0 0 1 0 0 x 1 1 0
1
1 1 1 1 0 0 0 1 1 0 0 x 0 0 1
1
1 1 1 0 0 0 0 1 1 0 0 x 0 0 1
0
0 1 0 0 0 0 0 0 1 0 0 x 1 0 0
0
0 1 1 0 0 0 1 1 0 1 0 x 0 0 1
0
1 0 0 0 0 0 0 0 0 1 0 x 0 1 0
0
0 0 1 0 0 0 0 0 1 1 0 x 0 0 1
30
32 3C 75 A0 00 00 04 34 F9 07 00 xx 48 42 35
12ns*
5
500ps*5 600ps*5 750ps*5 1000ps*5 Future use Initial 4 52 249 HITACHI *2 (ASCII-8bit code) H B 5
45
46 to 61 62 63
Superset information SPD revision Checksum for bytes 0 to 62 -A75B -B75B -10B
64 65 to 71 72 73 74 75
Manufacturer's JEDEC ID code Manufacturer's JEDEC ID code Manufacturing location Module part number Module part number Module part number
Data Sheet E0089H40 (Ver. 4.0)
6
HB54R1G9F2-A75B/B75B/10B
Byte No. 76 77 78 79 80 81 82 83 84 Function described Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number -A75B -B75B -10B 85 Module part number -A75B/B75B -10B 86 Module part number -A75B/B75B -10B 87 Module part number -A75B/B75B -10B 88 to 90 91 92 93 94 95 to 98 99 to 127 Module part number Revision code Revision code Manufacturing date Manufacturing date Module serial number Manufacturer specific data Bit7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x *3 *4 Bit6 0 1 0 1 0 1 0 0 1 1 0 0 0 0 1 1 0 0 0 0 x x Bit5 Bit4 1 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 1 1 1 1 x x 1 1 1 0 1 0 1 0 0 0 1 1 1 1 0 0 0 0 1 0 x x Bit3 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 x x Bit2 1 0 0 1 0 1 0 1 0 0 0 1 0 1 0 0 0 0 0 0 x x Bit1 Bit0 0 1 0 1 0 1 1 0 0 1 0 1 0 0 1 1 0 0 0 0 x x 0 0 1 1 1 0 0 1 1 0 1 1 0 1 0 0 0 0 0 0 x x Hex value 34 52 31 47 39 46 32 2D 41 42 31 37 30 35 42 42 20 20 30 20 xx xx Comments 4 R 1 G 9 F 2 -- A B 1 7 0 5 B B (Space) (Space) Initial (Space) Year code (BCD) Week code (BCD)
Notes: 1. All serial PD data are not protected. 0: Serial data, "driven Low", 1: Serial data, "driven High" These SPD are based on JEDEC Committee Ballot JC-42.5-99-129. 2. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows "J" on ASCII code.) 3. Bytes 95 through 98 are assembly serial number. 4. All bits of 99 through 127 are not defined ("1" or "0"). 5. These specifications are defined based on component specification, not module.
Data Sheet E0089H40 (Ver. 4.0)
7
HB54R1G9F2-A75B/B75B/10B
Block Diagram
VSS
/RS1 /RS0 DQS0 4 DQ0 to DQ3 RS DQS1 4 DQ8 to DQ11 RS DQS2 4 DQ16 to DQ19 RS DQS3 4 DQ24 to DQ27 RS DQS4 4 DQ32 to DQ35 RS DQS5 4 DQ40 to DQ43 RS DQS6 4 DQ48 to DQ51 RS DQS7 4 DQ56 to DQ59 RS DQS8 4 CB0 to CB3
RS RS RS RS RS RS RS RS RS
RS DM0/DQS9 RS DQS DQ /CS DM DQS DQ /CS DM DQ4 to DQ7 4
RS RS RS DM1/DQS10 DQS DQ /CS DM DQS DQ /CS DM DQ12 to DQ15 RS DM2/DQS11 DQS DQ /CS DM DQS DQ /CS DM DQ20 to DQ23 RS DM3/DQS12 DQS DQ /CS DM DQS DQ /CS DM DQ28 to DQ31 RS DM4/DQS13 DQS DQ /CS DM DQS DQ /CS DM DQ36 to DQ39 RS DM5/DQS14 DQS DQ /CS DM DQS DQ /CS DM DQ44 to DQ47 RS DM6/DQS15 DQS DQ /CS DM DQS DQ /CS DM DQ52 to DQ55 RS DM7/DQS16 DQS DQ /CS DM DQS DQ /CS DM DQ60 to DQ63 RS DM8/DQS17 DQS DQ /CS DM DQS DQ /CS DM CB4 to CB7 4 RS DQS DQ /CS DM DQS DQ /CS DM 4 RS DQS DQ /CS DM DQS DQ /CS DM 4 RS DQS DQ /CS DM DQS DQ /CS DM 4 RS DQS DQ /CS DM DQS DQ /CS DM 4 RS DQS DQ /CS DM DQS DQ /CS DM 4 RS DQS DQ /CS DM DQS DQ /CS DM 4 RS DQS DQ /CS DM DQS DQ /CS DM 4 RS DQS DQ /CS DM DQS DQ /CS DM DQS DQ /CS DM DQS DQ /CS DM
D0
D18
D9
D27
RS
D1
D19
D10
D28
RS
D2
D20
D11
D29
RS
D3
D21
D12
D30
RS
D4
D22
D13
D31
RS
D5
D23
D14
D32
RS
D6
D24
D15
D33
RS
D7
D25
D16
D34
RS
D8
D26
D17
D35
/S0 /S1 BA0 to BA1 A0 to A12 /RAS /CAS CKE0 CKE1 /WE
/RS0 -> /CS: SDRAMs D0 to D17 R E G I S T E R /RS1 -> /CS: SDRAMs D18 to D35 RBA0 to RBA1 -> BA0 to BA1: SDRAMs D0 to D35 RA0 to RA12 -> A0 to A12: SDRAMs D0 to D35 /RRAS -> /RAS: SDRAMs D0 to D35 /RCAS -> /CAS: SDRAMs D0 to D35 RCKE0 -> CKE: SDRAMs D0 to D17 RCKE1 -> CKE: SDRAMs D18 to D35 /RWE -> /WE: SDRAMs D0 to D35 /RESET
* D0 to D35: HM5425401TB U0: 2k bits EEPROM RS: 22 (DQ, DQS) PLL: CDC857 Register: SSTV16859 Serial PD SCL SCL SDA SDA
U0
A0 A1 A2
PCK /PCK
VCC, VCCQ VREF VSS VCCID open
D0 to D35 D0 to D35 D0 to D35
SA0 SA1 SA2 Notes: 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state.
CK0, /CK0 PLL* Note: Wire per Clock loading table/Wiring diagrams.
Data Sheet E0089H40 (Ver. 4.0)
8
HB54R1G9F2-A75B/B75B/10B
Differential Clock Net Wiring (CK0, /CK0)
0ns (nominal) SDRAM stack 120
PLL OUT1
CK0
120 IN
SDRAM stack 240 Register1
/CK0
120 C
OUT'N'
(Typically two registers per DIMM)
Feedback
240
Register2
Notes: 1. The clock delay from the input of the PLL clock to the input of any SDRAM or register willl be set to 0 ns (nominal). 2. Input, output and feedback clock lines are terminated from line to line as shown, and not from line to ground. 3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired in a similar manner. 4. Termination resistors for feedback path clocks are located after the pins of the PLL.
Data Sheet E0089H40 (Ver. 4.0)
9
HB54R1G9F2-A75B/B75B/10B
Pin Functions (1)
CK (CLK), /CK (/CLK) (input pin): The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross point of the CK rising edge and the VREF level. When a read operation, DQSs and DQs are referred to the cross point of the CK and the /CK. When a write operation, DMs and DQs are referred to the cross point of the DQS and the VREF level. DQSs for write operation are referred to the cross point of the CK and the /CK. /S (/CS) (input pin): When /S is Low, commands and data can be input. When /S is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. /RAS, /CAS, and /WE (input pins): These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. See "Command operation". A0 to A12 (input pins): Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the VREF level in a bank active command cycle. Column address (AY0 to AY9, AY11) is loaded via the A0 to the A9, the A11 at the cross point of the CK rising edge and the VREF level in a read or a write command cycle. This column address becomes the starting address of a burst operation. A10 (AP) (input pin): A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If A10 = High when a precharge command is issued, all banks are precharged. If A10 = Low when a precharge command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = High when read or write command, auto-precharge function is enabled. While A10 = Low, auto-precharge function is disabled. BA0, BA1 (input pin): BA0/BA1 are bank select signals. The memory array is divided into bank 0, bank 1, bank 2 and bank 3. If BA1 = Low and BA0 = Low, bank 0 is selected. If BA1 = High and BA0 = Low, bank 1 is selected. If BA1 = Low and BA0 = High, bank 2 is selected. If BA1 = High and BA0 = High, bank 3 is selected. CKE (input pin): CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the CKE is driven Low and exited when it resumes to High. The CKE level must be kept for 1 CK cycle (= LCKEPW) at least, that is, if CKE changes at the cross point of the CK rising edge and the VREF level with proper setup time tIS, at the next CK rising edge CKE level must be kept with proper hold time tIH.
Pin Functions (2)
DQ, CB (input and output pins): Data are input to and output from these pins. DQS (input and output pin): DQS provide the read data strobes (as output) and the write data strobes (as input). VCC and VCCQ (power supply pins): 2.5V is applied. (VCC is for the internal circuit and VCCQ is for the output buffer.) VCCSPD (power supply pin): 2.5V is applied (For serial EEPROM). VSS (power supply pin): Ground is connected. /RESET (input pin): LVCMOS reset input. When /RESET is low, all registers are reset and all outputs are low.
Detailed Operation Part, AC Characteristics and Timing Waveforms
Refer to the HM5425161B/HM5425801B/HM5425401B Series datasheet (E0086H10). DM pins of component device fixed to VSS level on the module board. DIMM /CAS latency = Device CL + 1 for registered type.
Data Sheet E0089H40 (Ver. 4.0)
10
HB54R1G9F2-A75B/B75B/10B
Electrical Specifications
Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC, VCCQ IOUT PT Topr Tstg Value -1.0 to +4.6 -1.0 to +4.6 50 18 0 to +55 -50 to +100 Unit V V mA W C C Note 1 1
Notes: 1. Respect to VSS. DC Operating Conditions (TA = 0 to +55C)
Parameter Supply voltage Symbol VCC, VCCQ VSS Input reference voltage Termination voltage DC Input high voltage DC Input low voltage DC Input signal voltage DC differential input voltage Ambient illuminance VREF VTT VIH VIL VIN (dc) min. 2.3 0 1.15 VREF - 0.04 VREF + 0.18 -0.3 -0.3 Typ 2.5 0 1.25 VREF -- -- -- -- -- max. 2.7 0 1.35 VREF + 0.04 VCCQ + 0.3 VREF - 0.18 VCCQ + 0.3 VCCQ + 0.6 100 Unit V V V V V V V V lx 1 1 1, 3 1, 4 5 6 Notes 1, 2
VSWING (dc) 0.36 -- --
Notes: 1. 2. 3. 4. 5. 6.
All parameters are referred to VSS, when measured. VCCQ must be lower than or equal to VCC. VIH is allowed to exceed VCC up to 4.6V for the period shorter than or equal to 5ns. VIL is allowed to outreach below VSS down to -1.0V for the period shorter than or equal to 5ns. VIN (dc) specifies the allowable dc execution of each differential input. VSWING (dc) specifies the input differential voltage required for switching.
Data Sheet E0089H40 (Ver. 4.0)
11
HB54R1G9F2-A75B/B75B/10B
DC Characteristics 1 (TA = 0 to 55C, VCC, VCCQ = 2.5V 0.2V, VSS = 0V)
Parameter Operating current (ACTV-PRE) Symbol ICC0 Grade -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B max. 3117 2928 2559 4107 3828 3459 1065 948 831 1857 1668 1479 1317 1128 939 2217 2028 1839 5367 5088 4809 5007 4728 4449 5007 4818 4359 525 516 507 Unit mA Test condition Notes
CKE VIH, tRC = min. 1, 2, 5 CKE VIH, BL = 2, CL = 3.5, tRC = min. CKE VIL
Operating current (ACTV-READICC1 PRE) Idle power down standby current ICC2P
mA
1, 2, 5
mA
4
Idle standby current Active power down standby current Active standby current Operating current (Burst read operation) Operating current (Burst write operation) Auto refresh current
ICC2N
mA
CKE VIH, /CS VIH
4
ICC3P
mA
CKE VIL CKE VIH, /CS VIH tRAS = max. CKE VIH, BL = 2, CL = 3.5 CKE VIH, BL = 2, CL = 3.5 tRFC = min., Input VIL or VIH Input VCC - 0.2V Input 0.2V.
3
ICC3N
mA
3
ICC4R
mA
1, 2, 5, 6
ICC4W
mA
1, 2, 5, 6
ICC5
mA
Self refresh current
ICC6
mA
Notes. 1. 2. 3. 4. 5. 6. 7.
These ICC data are measured under condition that DQ pins are not connected. One bank operation. One bank active. All banks idle. Command/Address transition once per one cycle. Data/Data mask transition twice per one cycle. The ICC data on this table are measured with regard to tCK = min. in general.
DC Characteristics 2 (TA = 0 to 55C, VCC, VCCQ = 2.5V 0.2V, VSS = 0V)
Parameter Input leakage current Output leakage current Output high voltage Output low voltage Symbol ILI ILO VOH VOL min. -10 -10 VTT + 0.76 -- max. 10 10 -- VTT - 0.76 Unit A A V V Test condition VCC VIN VSS VCC VOUT VSS IOH (max.) = -15.2mA IOL (min.) = 15.2mA Notes
Data Sheet E0089H40 (Ver. 4.0)
12
HB54R1G9F2-A75B/B75B/10B
Pin Capacitance (TA = 25C, VCC, VCCQ = 2.5V 0.2V)
Parameter Input capacitance Input capacitance Data and DQS input/output capacitance Symbol CI1 CI2 CO Pins max. Unit pF pF pF Notes 1, 3 1, 3 1, 2, 3
Address, /RAS, /CAS, /WE, 10 /S, CKE CK, /CK DQ, DQS, CB, DM 20 20
Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VCCQ/2, VOUT = 0.2V. 2. Dout circuits are disabled. 3. This parameter is sampled and not 100% tested. Timing Parameter Measured in Clock Cycle for Registered DIMM
Number of clock cycle Parameter Write to pre-charge command delay (same bank) Read to pre-charge command delay (same bank) Write to read command delay (to input all data) Burst stop command to write command delay (CL = 3) (CL = 3.5) Burst stop command to DQ High-Z (CL = 3) (CL = 3.5) Read command to write command delay (to output all data) (CL = 3) (CL = 3.5) Pre-charge command to High-Z (CL = 3) (CL = 3.5) Write command to data in latency Write recovery Register set command to active or register set command Self refresh exit to non-read command Self refresh exit to read command Power down entry Power down exit to command input CKE minimum pulse width Symbol tWPD tRPD tWRD tBSTW tBSTW tBSTZ tBSTZ tRWD tRWD tHZP tHZP tWCD tWR tMRD tSNR tSRD tPDEN tPDEX tCKEPW min. 3 + BL/2 BL/2 2 + BL/2 2 3 3 3.5 2 + BL/2 3 + BL/2 3 3.5 2 1 2 10 200 1 1 1 max.
Data Sheet E0089H40 (Ver. 4.0)
13
HB54R1G9F2-A75B/B75B/10B
Physical Outline
Unit: mm 133.35 0.15 128.95 4.80 (64.48) (DATUM -A-)
2.30
Component area (Front)
1 B 64.77 49.53 A 92
1.27 0.10
2 - 2.50 0.10
10.00
93 184
4.00 min
Component area (Back)
4.00 0.10
R 2.00
3.00 min
Detail A
2.50 0.20
Detail B 1.27 typ 6.62
0.20 0.15
(DATUM -A-) 2.175 R 0.90
6.35
3.80
1.00 0.05
1.80 0.10
Note: Tolerance on all dimensions 0.13 unless otherwise specified.
ECA-TS2-0052-01
Data Sheet E0089H40 (Ver. 4.0)
14
43.18 0.15
17.80
HB54R1G9F2-A75B/B75B/10B
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. In particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. When re-packing memory modules, be sure the modules are not touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
MDE0202
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
CME0107
Data Sheet E0089H40 (Ver. 4.0)
15
HB54R1G9F2-A75B/B75B/10B
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
M01E0107
Data Sheet E0089H40 (Ver. 4.0)
16

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